Introduction to Digital Systems. Combinational Circuits. Digital Integrated Circuits. Lecture 1

Introduction to Digital Systems. Combinational Circuits. Digital Integrated Circuits.
Lecture 1
Dana Utebayeva

Outline
Basic concepts
Simple gates
Completeness
Logic functions
Expressing logic functions
Equivalence
Boolean algebra
Boolean identities
Logical equivalence
Logic Circuit Design Process
Deriving logical expressions
Sum-of-products form
Product-of-sums form
Simplifying logical expressions
Algebraic manipulation
Karnaugh map method
Quine-McCluskey method
Generalized gates
Multiple outputs
Implementation using other gates (NAND and XOR)

Introduction
Hardware consists of a few simple building blocks
These are called logic gates
AND, OR, NOT, …
NAND, NOR, XOR, …
Logic gates are built using transistors
NOT gate can be implemented by a single transistor
AND gate requires 3 transistors
Transistors are the fundamental devices
Pentium consists of 3 million transistors
Compaq Alpha consists of 9 million transistors
Now we can build chips with more than 100 million transistors

Basic Concepts
Simple gates
AND
OR
NOT
Functionality can be expressed by a truth table
A truth table lists output for each possible input combination
Other methods
Logic expressions
Logic diagrams

Basic Concepts (cont’d)
Additional useful gates
NAND
NOR
XOR
NAND = AND + NOT
NOR = OR + NOT
XOR implements exclusive-OR function
NAND and NOR gates require only 2 transistors
AND and OR need 3 transistors!

Basic Concepts (cont’d)
Number of functions
With N logical variables, we can define
22N functions
Some of them are useful
AND, NAND, NOR, XOR, …
Some are not useful:
Output is always 1
Output is always 0
“Number of functions” definition is useful in proving completeness property

Basic Concepts (cont’d)
Complete sets
A set of gates is complete
if we can implement any logical function using only the type of gates in the set
You can uses as many gates as you want
Some example complete sets
{AND, OR, NOT} Not a minimal complete set
{AND, NOT}
{OR, NOT}
{NAND}
{NOR}
Minimal complete set
A complete set with no redundant elements.

Basic Concepts (cont’d)
Proving NAND gate is universal

Basic Concepts (cont’d)
Proving NOR gate is universal

Logic Chips
Basic building block:
Transistor
Three connection points
Base
Emitter
Collector
Transistor can operate
Linear mode
Used in amplifiers
Switching mode
Used to implement digital circuits

Logic Chips (cont’d)
NOT
NAND
NOR

Logic Chips (cont’d)
Low voltage level: < 0.4V
High voltage level: > 2.4V
Positive logic:
Low voltage represents 0
High voltage represents 1
Negative logic:
High voltage represents 0
Low voltage represents 1
Propagation delay
Delay from input to output
Typical value: 5-10 ns

Logic Chips (cont’d)

Logic Chips (cont’d)
Integration levels
SSI (small scale integration)
Introduced in late 1960s
1-10 gates (previous examples)
MSI (medium scale integration)
Introduced in late 1960s
10-100 gates
LSI (large scale integration)
Introduced in early 1970s
100-10,000 gates
VLSI (very large scale integration)
Introduced in late 1970s
More than 10,000 gates

Logic Functions
Logical functions can be expressed in several ways:
Truth table
Logical expressions
Graphical form
Example:
Majority function
Output is one whenever majority of inputs is 1
We use 3-input majority function

Logic Functions (cont’d)
3-input majority function
A B C F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Logical expression form
F = A B + B C + A C

Logical Equivalence
All three circuits implement F = A B function

Logical Equivalence (cont’d)
Proving logical equivalence of two circuits
Derive the logical expression for the output of each circuit
Show that these two expressions are equivalent
Two ways:
You can use the truth table method
For every combination of inputs, if both expressions yield the same output, they are equivalent
Good for logical expressions with small number of variables
You can also use algebraic manipulation
Need Boolean identities

Logical Equivalence (cont’d)
Derivation of logical expression from a circuit
Trace from the input to output
Write down intermediate logical expressions along the path

Logical Equivalence (cont’d)
Proving logical equivalence: Truth table method
A B F1 = A B F3 = (A + B) (A + B) (A + B)
0 0 0 0
0 1 0 0
1 0 0 0
1 1 1 1

Thanks for your attention

LECTURE 2

FUNDAMENTALS
OF LOGICAL DESIGN
SIS 2
“Binary systems”
[email protected]
Dana Utebayeva

DECIMAL TO BINARY CONVERSION
Convert Decimal Number to a Binary Number:
Decimal
Binary
1110011100000
7392

QUIZ for SIS Project 1
Conversion of Decimal Number to a Binary Number:
Dana Zh. Utebayeva: https://docs.google.com/forms/d/e/1FAIpQLSeKQMn0v_6GEpZ-ROuIxY7bV…
опубликовано в 13507 Fundamentals of Logic Design (Утебаева Д..) 2021-2022/1 или Общий в Tuesday, September 14, 2021 12:19:40 PM

FUNDAMENTALS
OF LOGICAL DESIGN
Lecture 2
“Number systems and Codes”
[email protected]
Dana Utebayeva

Goal of the lecture is to be familiar with number systems and code in digital electronics.

Outline of Lecture
Counting in Decimal and Binary
Place Value
Binary to Decimal Conversion
Decimal to Binary Conversion
Electronic Translators
Hexadecimal Numbers
Octal Numbers

Number systems
Radix and subscript

COUNTING IN
DECIMAL AND BINARY
Number System -
Code using symbols that refer to
a number of items.
Decimal Number System -
Uses ten symbols (base 10 system)
Binary System -
Uses two symbols (base 2 system)

Generalized approach of Number systems
A number with a decimal point is represented by series of coefficients

PLACE VALUE
Numeric value of symbols in different positions.
Example - Place value in binary system:
Binary
8s
4s
2s
1s
Number
Place Value
Yes
Yes
No
No
1
0
0
1
RESULT: Binary 1100 = decimal 8 + 4 + 0 + 0 = decimal 12

BINARY TO DECIMAL CONVERSION
Convert Binary Number 110011 to a Decimal Number: 32 + 16 + 0 + 0 + 2 + 1 = 51
1 1 0 0 1 1
Decimal
Binary

TEST
Convert the following binary numbers into decimal numbers:
Binary 1001 =
9
Binary 1111 =
Binary 0010 =
15
2

DECIMAL TO BINARY CONVERSION
Divide by 2 Process
Decimal #
13 ÷ 2 = 6 remainder 1
6 ÷ 2 = 3 remainder 0
3 ÷ 2 = 1 remainder 1
1 ÷ 2 = 0 remainder 1
1
1
0
1

TEST
Convert the following decimal numbers into binary:
Decimal 11 =
Decimal 4 =
Decimal 17 =
1011
0100
10001

ELECTRONIC TRANSLATORS
Devices that convert from decimal to binary numbers and from binary to decimal numbers.
Encoders -
translates from decimal to binary
Decoders -
translates from binary to decimal

ELECTRONIC ENCODER - DECIMAL TO BINARY
0
Decimal
to
Binary
Encoder
Binary output
Decimal input
0 0 0 0
5
0 1 0 1
7
0 1 1 1
0 0 1 1
Encoders are available in IC form.
This encoder translates from decimal input to binary (BCD) output.

Binary-to-
7-Segment
Decoder/
Driver
ELECTRONIC DECODING: BINARY TO DECIMAL
Binary input
0 0 0 0
Decimal output
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
Electronic decoders are available in IC form.
This decoder translates from binary to decimal.
Decimals are shown on an 7-segment LED display.
This decoder also drives the 7-segment display.

Uses 16 symbols -Base 16 System
0-9, A, B, C, D, E, F
Decimal
1
9
10
15
16
Binary
0001
1001
1010
1111
10000
Hexadecimal
1
9
A
F
10
HEXADECIMAL NUMBER SYSTEM

Hexadecimal to Binary Conversion
Hexadecimal C 3
Binary 1100 0011
Binary 1110 1010
Hexadecimal E A
Binary to Hexadecimal Conversion
HEXADECIMAL AND BINARY CONVERSIONS

DECIMAL TO HEXADECIMAL CONVERSION
Divide by 16 Process
Decimal #
47 ÷ 16 = 2 remainder 15
2 ÷ 16 = 0 remainder 2
F
2

HEXADECIMAL TO DECIMAL CONVERSION
Convert hexadecimal number 2DB to a decimal number
512 + 208 + 11 = 731
2 D B
Hexadecimal
Decimal
Place Value
256s 16s 1s
(256 x 2) (16 x 13) (1 x 11)

TEST
Convert Hexadecimal number A6 to Binary
Convert Hexadecimal number 16 to Decimal
Convert Decimal 63 to Hexadecimal
63 =
16 =
A6 =
1010 0110 (Binary)
22 (Decimal)
3F (Hexadecimal)

OCTAL NUMBERS
Uses 8 symbols -Base 8 System
0, 1, 2, 3, 4, 5, 6, 7
Decimal
1
6
7
8
9
Octal
1
6
7
10
11
Binary
001
110
111
001 000
001 001

PRACTICAL SUGGESTION ON NUMBER SYSTEM CONVERSIONS
Use a scientific calculator
Most scientific calculators have DEC, BIN,
OCT, and HEX modes and can either
convert between codes or perform
arithmetic in different number systems.
Most scientific calculators also have other
functions that are valuable in digital
electronics such as AND, OR, NOT,
XOR, and XNOR logic functions.

1) first page (Names, Title: “Binary systems”)
2) Outline (План)
3) Part I: (images from your “конспект”)
4) Part II: Upload/insert your screens from your Quiz
5) Part: Assignments: screens from your copybook
6) About calculators
Deadline: Monday till 18.oo (20.09.2021)
SIS project 1

Attendance for Lecture 2
Dana Zh. Utebayeva: https://docs.google.com/forms/d/e/1FAIpQLSfotGeOUvqjykd78SYCT_WEU…
опубликовано в 13507 Fundamentals of Logic Design (Утебаева Д..) 2021-2022/1 или Общий в Tuesday, September 14, 2021 1:46:25 PM

LECTURE 3-4

Outline
Binary numbers
Logic States
Implementation
The Buffer Logic Gate using n-p-n transistors
Logic Gates using transistors
Logic functions
Expressing logic functions
Building block diagrams
Boolean algebra
Boolean algebra laws
Logic Circuit Design Process
Deriving logical expressions
Sum-of-products form
Product-of-sums form
Generalized gates
Multiple outputs
Implementation using other gates (NAND and XOR)

POS – product of sums

Logic Gates
Simple gates
AND
OR
NOT
Functionality can be expressed by a truth table
A truth table lists output for each possible input combination
Other methods
Logic expressions
Logic diagrams

Basic Concepts (cont’d)
Additional useful gates
NAND
NOR
XOR
NAND = AND + NOT
NOR = OR + NOT
XOR implements exclusive-OR function
NAND and NOR gates require only 2 transistors
AND and OR need 3 transistors!

Basic Concepts (cont’d)
Number of functions
With N logical variables, we can define
22N functions
Some of them are useful
AND, NAND, NOR, XOR, …
Some are not useful:
Output is always 1
Output is always 0
“Number of functions” definition is useful in proving completeness property

Basic Concepts (cont’d)
Complete sets
A set of gates is complete
if we can implement any logical function using only the type of gates in the set
You can uses as many gates as you want
Some example complete sets
{AND, OR, NOT} Not a minimal complete set
{AND, NOT}
{OR, NOT}
{NAND}
{NOR}
Minimal complete set
A complete set with no redundant elements.

Basic Concepts (cont’d)
Proving NAND gate is universal

Basic Concepts (cont’d)
Proving NOR gate is universal

Logic Chips
Basic building block:
Transistor
Three connection points
Base
Emitter
Collector
Transistor can operate
Linear mode
Used in amplifiers
Switching mode
Used to implement digital circuits

Logic Chips (cont’d)
NOT
NAND
NOR

Logic Chips (cont’d)
Low voltage level: < 0.4V
High voltage level: > 2.4V
Positive logic:
Low voltage represents 0
High voltage represents 1
Negative logic:
High voltage represents 0
Low voltage represents 1
Propagation delay
Delay from input to output
Typical value: 5-10 ns

Logic Chips (cont’d)

Logic Chips (cont’d)
Integration levels
SSI (small scale integration)
Introduced in late 1960s
1-10 gates (previous examples)
MSI (medium scale integration)
Introduced in late 1960s
10-100 gates
LSI (large scale integration)
Introduced in early 1970s
100-10,000 gates
VLSI (very large scale integration)
Introduced in late 1970s
More than 10,000 gates

Logic Functions
Logical functions can be expressed in several ways:
Truth table
Logical expressions
Graphical form
Example:
Majority function
Output is one whenever majority of inputs is 1
We use 3-input majority function

Logic Functions (cont’d)
3-input majority function
A B C F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Logical expression form
F = A B + B C + A C

Logical Equivalence
All three circuits implement F = A B function

Logical Equivalence (cont’d)
Proving logical equivalence of two circuits
Derive the logical expression for the output of each circuit
Show that these two expressions are equivalent
Two ways:
You can use the truth table method
For every combination of inputs, if both expressions yield the same output, they are equivalent
Good for logical expressions with small number of variables
You can also use algebraic manipulation
Need Boolean identities

Logical Equivalence (cont’d)
Derivation of logical expression from a circuit
Trace from the input to output
Write down intermediate logical expressions along the path

Logical Equivalence (cont’d)
Proving logical equivalence: Truth table method
A B F1 = A B F3 = (A + B) (A + B) (A + B)
0 0 0 0
0 1 0 0
1 0 0 0
1 1 1 1

Thanks for your attention

LECTURE 4

#3 Boolean Algebra and Digital Logic Gates.
#4 Combinational logic design. Completely and Incompletely Specified Logic Functions. Design of a combinational Circuits.
Lecture 3 - 4
Dana Utebayeva

Outline
Binary numbers
Logic States
Implementation
The Buffer Logic Gate using n-p-n transistors
Logic Gates using transistors
Logic functions
Expressing logic functions
Building block diagrams
Boolean algebra
Boolean algebra laws
Logic Circuit Design Process
Deriving logical expressions
Sum-of-products form
Product-of-sums form
Generalized gates
Multiple outputs
Implementation using other gates (NAND and XOR)

Basic Concepts (cont’d)
Number of functions
With N logical variables, we can define
22N functions
Some of them are useful
AND, NAND, NOR, XOR, …
Some are not useful:
Output is always 1
Output is always 0
“Number of functions” definition is useful in proving completeness property

Basic Concepts (cont’d)
Complete sets
A set of gates is complete
if we can implement any logical function using only the type of gates in the set
You can uses as many gates as you want
Some example complete sets
{AND, OR, NOT} Not a minimal complete set
{AND, NOT}
{OR, NOT}
{NAND}
{NOR}
Minimal complete set
A complete set with no redundant elements.

Basic Concepts (cont’d)
Proving NAND gate is universal

Basic Concepts (cont’d)
Proving NOR gate is universal

Logic Chips
Basic building block:
Transistor
Three connection points
Base
Emitter
Collector
Transistor can operate
Linear mode
Used in amplifiers
Switching mode
Used to implement digital circuits

Logic Chips (cont’d)
NOT
NAND
NOR

Logic Chips (cont’d)
Low voltage level: < 0.4V
High voltage level: > 2.4V
Positive logic:
Low voltage represents 0
High voltage represents 1
Negative logic:
High voltage represents 0
Low voltage represents 1
Propagation delay
Delay from input to output
Typical value: 5-10 ns

Logic Chips (cont’d)

Logic Chips (cont’d)
Integration levels
SSI (small scale integration)
Introduced in late 1960s
1-10 gates (previous examples)
MSI (medium scale integration)
Introduced in late 1960s
10-100 gates
LSI (large scale integration)
Introduced in early 1970s
100-10,000 gates
VLSI (very large scale integration)
Introduced in late 1970s
More than 10,000 gates

Logic Functions
Logical functions can be expressed in several ways:
Truth table
Logical expressions
Graphical form
Example:
Majority function
Output is one whenever majority of inputs is 1
We use 3-input majority function

Logic Functions (cont’d)
3-input majority function
A B C F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Logical expression form
F = A B + B C + A C

Logical Equivalence
All three circuits implement F = A B function

Logical Equivalence (cont’d)
Proving logical equivalence of two circuits
Derive the logical expression for the output of each circuit
Show that these two expressions are equivalent
Two ways:
You can use the truth table method
For every combination of inputs, if both expressions yield the same output, they are equivalent
Good for logical expressions with small number of variables
You can also use algebraic manipulation
Need Boolean identities

Logical Equivalence (cont’d)
Derivation of logical expression from a circuit
Trace from the input to output
Write down intermediate logical expressions along the path

Logical Equivalence (cont’d)
Proving logical equivalence: Truth table method
A B F1 = A B F3 = (A + B) (A + B) (A + B)
0 0 0 0
0 1 0 0
1 0 0 0
1 1 1 1

Thanks for your attention

LECTURE 5

«СРС»: SIS, Practice class and Lab class assignments explanation
#5 Combinational and Sequential Circuit. Adders. Subtractors. Comparators.
Lecture 5
Dana Utebayeva

Outline
«СРС» SIS assignments explanation
Practice class
Lab class
SIS assignments explanation
Boolean Identities/Postulates/laws
Expressing logic functions
Building block diagrams
Simplification Using Boolean Identities
Standard Representations
Minterm
Maxterm
Combinational and Sequential circuits
Adders
Comparators
Full Subtractor

Boolean Identities / Postulates / laws
Boolean Laws

Problem 2
(a) Implementation of f= ABCD + ABCD + BC(b) implementation of the simplified function f= BC + DImplementation of Boolean function using logic gates

Simplification Using Boolean Identities
f= ABCD + ABCD + BC

Complement of a Boolean Function
(А + В + С)

Complement of a Boolean Function
f= C'(AB + A'B'D + A'BD')
f= C(AB + ABD + ABD)

Combinational and Sequential circuits

Full Adder

Logic Diagram of Full Adder

Two-bit Comparator

Full Subtractor

Logic Chips (cont’d)
Integration levels
SSI (small scale integration)
Introduced in late 1960s
1-10 gates (previous examples)
MSI (medium scale integration)
Introduced in late 1960s
10-100 gates
LSI (large scale integration)
Introduced in early 1970s
100-10,000 gates
VLSI (very large scale integration)
Introduced in late 1970s
More than 10,000 gates

LECTURE 6

Multiplexer design Procedure and applications
Lecture 6
Utebayeva dana

Truth table for MUX
Truth table for 4-to-1 MUX

LECTURE 7

Demultiplexers and their Applications
Lecture 7, By dana Utebayeva

DEMUX DEMULTIPLEXER

MUX and DEMUX applications

MUX and DEMUX applications

MUX and DEMUX applications

LECTURE 8 K-MAP K MAP KMAP

Introduction to Karnaugh map (k-map)
СРС (SIS) by Dana Utebayeva

LECTURE 9

Sequential Circuit. Sequential logic design. Flip-Flop. Counters
Lecture 9
By Dana Utebayeva

Sequential Circuit. Sequential logic design. Flip-Flop. Counters

In Sequential Circuit, the Present Output depends on the Present Input as well as Past output / outputs

Cascaded NOT logic gate

The basic storage element is called latch

LECTURE 11-12

Lecture 10-11
MICROCOMPUTER ARCHITECTURE
Memory
ADC and DAC

ADC and DAC
1.1 Basic Blocks of a Microcomputer
1.2 Typical Microcomputer Architecture
1.3 Single-Chip Microprocessor
1.4 Program Execution by Conventional Microprocessors
1.5 Program Execution by typical 32-bit Microprocessors
1.6 Scalar and Superscalar Microprocessors
1.7 RISC vs. CISC
Outline

ADC

ADC and DAC
Work use of ADC and DAC
Sound Waves Electrical Voltage Binary Data Electrical Voltage Sound Waves

Need Conversation

ADC in Multisim

DAC
DAC scheme DAC circuit

A microcomputer has three basic blocks: a central processing unit (CPU), a memory unit,
and an input/output (I/O) unit.
The CPU(microprocessor) executes all the instructions and performs arithmetic and logic operations on data.
A memory unit stores both data and instructions. The memory section typically
contains ROM and RAM chips.
A system bus (comprised of several wires) connects these blocks.
2.1 Basic Blocks of a Microcomputer

2.1 Basic Blocks of a Microcomputer
System bus

In a single-chip microcomputer, these three elements are on one chip, whereas
in a single-chip microprocessor, separate chips are required for memory and I/O.
2.1 Basic Blocks of a Microcomputer

2.2 Typical Microcomputer Architecture
Simplified version of typical microprocessor

The microcomputer’s system bus contains three buses, address, data, and control bus
When a memory or an I/O chip receives data from the microprocessor, it is called a WRITE operation, and data is written into a selected memory location or an I/O port (register).
When a memory or an I/O chip sends data to the microprocessor, it is called a READ operation, and data is read from a selected memory location or an I/O port.
2.2.1 System Bus

The Address Bus
Unidirectional bus: Information transfer takes place in only one direction, from the microprocessor to the memory or I/O elements.
Typically 20 to 32 bits long.
The size of the address bus determines the
total number of memory addresses available
2.2.1 System Bus
For example : microprocessor with 32 address pins can
generate 232 = 4,294,964,296 bytes

The data bus,
bidirectional bus: data can flow in both directions, that is, to or from the microprocessor.
The size of the data bus varies from one microprocessor to another.
2.2.1 System Bus

The control bus
consists of a number of signals that are used to synchronize operation of the individual microcomputer elements.
2.2.1 System Bus
Is it Unidirectional or bidirectional bus ??

The system clock signals are contained in the control bus.
The number of cycles per second (hertz, abbreviated Hz) is referred to as the clock frequency.
clock cycle = 1/f where f is the clock frequency.
clock frequency determines the speed of the microcomputer.
2.2.2 Clock Signals

The microprocessor is the CPU of the microcomputer
The logic inside the microprocessor chip can be divided into three main areas: the
register section, the control unit, and the arithmetic-logic unit (ALU).
2.3 Single-Chip Microprocessor

The number, size, and types of registers vary from one microprocessor to another.
Basic Microprocessor Registers There are four basic microprocessor registers: instruction register, program counter, memory address register, and accumulator.
2.3.1 Register Section

Instruction register (IR) :
The instruction register stores instructions.
The word size of the microprocessor determines the size of the instruction register. For example, a 32-bit microprocessor has a 32-bit instruction register.
2.3.1 Register Section

Program Counter (PC):
The program counter contains the address of the instruction or operation code (op-code).
The program counter normally contains the address of the next instruction to be executed.
The size of the program counter is determined by the size of the address bus.
2.3.1 Register Section

How Program Counter is Work ?
Upon activating the microprocessor’s RESET input, the address of the first instruction to be executed is loaded into the program counter.
To execute an instruction, the microprocessor typically places the contents of the program counter on the address bus and reads (“fetches”) the contents of this address(i.e., instruction) from memory
The program counter contents are incremented automatically by the microprocessor’s internal logic. Microprocessor executes a program sequentially, unless the program contains an instruction such as a JUMP instruction, which changes the sequence.
2.3.1 Register Section

Memory Address Register (MAR).
The memory address register contains the address of data. The microprocessor uses the address, which is stored in the memory address register, as a direct pointer to memory. The contents of the address is the actual data that is being transferred.
2.3.1 Register Section

General Purpose Register (GPR). For an 8-bit microprocessor, the general-purpose register is called the accumulator.
It stores the result after most ALU operations.
These 8-bit microprocessors have instructions to shift or rotate the accumulator one bit to the right or left through the carry flag.
In16- and 32-bit microprocessors the accumulator is replaced by a GPR.
any GPR can be used as an accumulator.
2.3.1 Register Section

General Purpose Register (GPR).
The term general-purpose comes from the fact that these registers can hold data, memory
addresses, or the results of arithmetic or logic operations.
Most registers are general-purpose, but some, such as the program counter (PC),are provided for dedicated functions.
2.3.1 Register Section

Other Microprocessor Registers such as general-purpose registers, index register, status register and stack pointer register.
general-purpose registers speeds up the execution of a program because the microprocessor does not have to read data from external memory via the data bus if data is stored in one of its general-purpose registers.
Index Register is typically used as a counter in address modification for an instruction or for general storage functions. Used to access tables or arrays of data.
Status Register( a processor status word register or condition code register, contains individual bits, with each bit having special significance. The bits in the status register are called flags.
2.3.1 Register Section

Flags Type
A carry flag is used to reflect whether or not the result generated by an arithmetic operation is greater than the microprocessor’s word size.
2.3.1 Register Section
Auxiliary carry flag

Flags Type
A zero flag is used to show whether the result of an operation is zero. It is set to1 if the result is zero, and it is reset to 0 if the result is nonzero.
A parity flag is set to 1 to indicate whether the result of the last operation contains either an even number of 1’s (even parity) or an odd number of 1’s (odd parity), depending on the microprocessor.
2.3.1 Register Section

Flags Type
A sign flag (sometimes called a negative flag) is used to indicate whether the result of the last operation is positive(set to 0) or negative(set to 1)
Overflow flag arises from representation of the sign flag by the most significant bit of a word in signed binary operation. The overflow flag is set to1 if the result of an arithmetic operation is too big for the microprocessor’s maximum word size, otherwise it is reset to 0
2.3.1 Register Section

EXAMPLE :
Find the sign,carry,zero,overflow,and parity even flag for the following arithmetic sign number:
(11110000)+(10100001) =10010001
SF =1 ,CF=1 ,ZF=0 ,OF=0 ,PF=0
2.3.1 Register Section

Stack Pointer Register A stack consists of a number of RAM locations set aside for reading data from or writing data into these locations and is typically used by subroutines
Two instructions, PUSH and POP, are usually available with a stack. The PUSH operation
is defined as writing to the top or bottom of the stack, whereas the POP operation means reading from the top or bottom of the stack.
2.3.1 Register Section

2.3.1 Register Section
Push operation when accessing a stack from the bottom

2.3.1 Register Section

2.3.1 Register Section

2.3.1 Register Section

The main purpose of the control unit is to read and decode instructions from the program memory.
To execute an instruction, the control unit steps through the appropriate blocks of the ALU based on the op-codes contained in the instruction register.
2.3.2 Control Unit

Control Signal Actions
RESET. This input is common to all microprocessors. When this input pin is driven HIGH or LOW (depending on the microprocessor), the program counter is loaded with a predefined address specified by the manufacturer.
2.3.2 Control Unit

Control Signal Actions
READ/WRITE (R/W) This output line is common to all microprocessors. The status of this line tells the other microcomputer elements whether the microprocessor is performing a READ or a WRITE operation. A HIGH signal on this line indicates a READ operation, and a LOW indicates a WRITE operation.
2.3.2 Control Unit

Control Signal Actions
READY, This is an input to a microprocessor. Slow devices (memory and I/O) use this signal to gain extra time to transfer data to or receive data from a microprocessor. The READY signal is usually an active low signal; that is, LOW indicates that the microprocessor is ready. Therefore, when the microprocessor selects a slow device, the device places a LOW on the READY pin. The microprocessor responds by suspending all its internal operations and enters a WAIT state. When the device is ready to send or receive data, it removes the READY signal. The microprocessor comes out of the WAIT state and performs the appropriate operation.
2.3.2 Control Unit

Control Signal Actions
Interrupt Request (INT or IRQ). The external I/O devices can interrupt the microprocessor via this input pin on the microprocessor chip. When this signal is activated by the external devices, the microprocessor jumps to a special program called the interrupt service routine. This program is normally written by the user for performing tasks that the interrupting device wants the microprocessor to carry out. After completing this program, the microprocessor returns to the main program it was executing when the interrupt occurred.
2.3.2 Control Unit

The ALU performs all the data manipulations, such as arithmetic and logic operations, inside a microprocessor. The size of the ALU conforms to the word length of the microcomputer.
ALU Functions:
1.Binary addition and logic operations
2. Finding the one’s complement of data
3. Shifting or rotating the contents of a general-purpose register 1 bit to the left or right through a carry
2.3.3 Arithmetic-Logic Unit

Simple Microprocessor
2.3.4 Functional Representations of Simple and Typical Microprocessors

Buffer Register : Stores any data read from memory for further processing by the ALU.
2.3.4 Functional Representations of Simple and Typical Microprocessors

Typical Microprocessor
2.3.4 Functional Representations of Simple and Typical Microprocessors

The Pentium contains two instruction pipelines: the U-pipe and the V-pipe. The U-pipe can execute all integer and floating-point instructions. The V-pipe can execute simple integer instructions
The Pentium contains two separate cache memories: code cache and data cache.

The control unit performs two basic operations:
instruction interpretation
and instruction sequencing.
2.3.5 Simplified Explanation of Control Unit design

There are two methods for designing a control unit:
2.3.5 Simplified Explanation of Control Unit design

How incrementing the contents of the register by 1 is done in microprogramming
control ??
(see figures in next slides)
2.3.5 Simplified Explanation of Control Unit design

2.3.5 Simplified Explanation of Control Unit design
Transferring register contents to a data bus

2.3.5 Simplified Explanation of Control Unit design

2.3.5 Simplified Explanation of Control Unit design

2.3.5 Simplified Explanation of Control Unit design

2.3.5 Simplified Explanation of Control Unit design

The following three steps for completing the instruction:
1.Fetch. The microprocessor fetches (instruction read) the instruction from the main memory (external to the microprocessor) into the instruction register.
2. Decode. The microprocessor decodes or translates the instruction using the control unit. The control unit inputs the contents of the instruction register, and then decodes (translates) the instruction to determine the instruction type.
3. Execute. The microprocessor executes the instruction using the control unit. To accomplish the task, the control unit generates a number of enable signals required by the instruction.
2.4 Program Execution by Conventional Microprocessors

For example, suppose that it is desired to add the contents of two registers, X and Y, and store the result in register Z. To accomplish this, a conventional microprocessor performs the following steps:
1. The microprocessor fetches the instruction into the instruction register.
2. The control unit (CU) decodes the contents of the instruction register.
3. The CU executes the instruction by generating enable signals for the register and ALU sections to perform the following:
a. The CU transfers the contents of registers X and Y from the Register section into the ALU.
b. The CU commands the ALU to ADD.
c. The CU transfers the result from the ALU into register Z of the register section.
2.4 Program Execution by Conventional Microprocessors

Enhancement in 32-bit microprocessors (like Pentium) include : cache memory, memory
management, pipelining, floating-point arithmetic, and branch prediction.
Cache memory is a high-speed read/write memory implemented as on-chip
hardware in typical 32-bit microprocessors in order to increase processing rates. This topic
is covered in more detail in Chapter 3.
2.5 Program Execution by typical 32-bit Microprocessors

Memory management allows programmers to write programs much larger than those that could fit in the main memory space available to the microprocessors; the programs are simply stored on a secondary device, such as a hard disk. This topic is covered in more detail in Chapter 3.
2.5 Program Execution by typical 32-bit Microprocessors

Basic Concept
2.5.1 Pipelining
Hi is Hardware designed to perform activity Ai

2.5.1 Pipelining

Two Kind of Pipelining:
Arithmetic operations and instruction execution.
2.5.1 Pipelining

Arithmetic Pipelines
Consider the process of adding two floating-point numbers x =0.9234 * 104 and y = 0.48 * 10 2.
First: exponents of x and y are unequal.
Second: exponent alignment.
Third: Perform the addition
Fourth: Normalize the final answer
2.5.1 Pipelining

Pipelined floating-point add/subtract unit
segment

Instruction Pipelines
Instruction cycle typically involves the
following activities:
1. Instruction fetch -?needs five clocks to complete
2. Instruction decode
3. Operand fetch (Data Read)
4. Operation execution
5. Result routing.
2.5.1 Pipelining

Five-segment instruction pipeline

Example of the execution of a stream of five instructions: 11,12,13,14, and 15, in which I3 is a conditional branch instruction.
2.5.1 Pipelining

This allows these microprocessors to anticipate jumps of the instruction flow ahead of time.
2.5.2 Branch Prediction Feature

To accomplish this, the Pentium includes on-chip hardware called the Branch Unit (BU). The BU contains the branch execution unit (BEU) and the branch prediction unit (BPU). Whenever the Pentium encounters a conditional branch instruction, it sends it to the BU for execution. The BU evaluates the instruction’s branch condition using the BEU and determines whether the branch should or should not be taken. Once the BU determines the branch condition, it calculates the starting address (Branch target) of the next block of code to be executed. The Pentium then starts fetching code at the new address.
2.5.2 Branch Prediction Feature

Scalar processors such as the 80486 can execute one instruction per cycle.
The 80486 contains only one pipeline.
Superscalar microprocessors, can execute
more than one instruction per cycle. These microprocessors contain more than one pipeline.
The Pentium, a superscalar microprocessor, contains two independent pipelines. This
allows the Pentium to execute two instructions per cycle.
2.6 Scalar and Superscalar Microprocessors

There are two types of microprocessor architectures: RISC and CISC.
RISC stand for (reduced instruction set computer) and CISC for (complex instruction set computer)
2.7 RISC vs. CISC

2.7 RISC vs. CISC

Intel’s original Pentium is a CISC microprocessor. Intel Pentium Pro and other succeeding members of the Pentium family and Motorola 68060 use a combination of RISC and CISC architectures for providing high performance. The Pentium Pro and other succeeding
2.7 RISC vs. CISC

LECTURE 11-12

Lecture 10-11
MICROCOMPUTER ARCHITECTURE
Memory
ADC and DAC

ADC and DAC
1.1 Basic Blocks of a Microcomputer
1.2 Typical Microcomputer Architecture
1.3 Single-Chip Microprocessor
1.4 Program Execution by Conventional Microprocessors
1.5 Program Execution by typical 32-bit Microprocessors
1.6 Scalar and Superscalar Microprocessors
1.7 RISC vs. CISC
Outline

Flags Type
A zero flag is used to show whether the result of an operation is zero. It is set to1 if the result is zero, and it is reset to 0 if the result is nonzero.
A parity flag is set to 1 to indicate whether the result of the last operation contains either an even number of 1’s (even parity) or an odd number of 1’s (odd parity), depending on the microprocessor.
2.3.1 Register Section

Flags Type
A sign flag (sometimes called a negative flag) is used to indicate whether the result of the last operation is positive(set to 0) or negative(set to 1)
Overflow flag arises from representation of the sign flag by the most significant bit of a word in signed binary operation. The overflow flag is set to1 if the result of an arithmetic operation is too big for the microprocessor’s maximum word size, otherwise it is reset to 0
2.3.1 Register Section

EXAMPLE :
Find the sign,carry,zero,overflow,and parity even flag for the following arithmetic sign number:
(11110000)+(10100001) =10010001
SF =1 ,CF=1 ,ZF=0 ,OF=0 ,PF=0
2.3.1 Register Section

Stack Pointer Register A stack consists of a number of RAM locations set aside for reading data from or writing data into these locations and is typically used by subroutines
Two instructions, PUSH and POP, are usually available with a stack. The PUSH operation
is defined as writing to the top or bottom of the stack, whereas the POP operation means reading from the top or bottom of the stack.
2.3.1 Register Section

2.3.1 Register Section

2.3.1 Register Section

2.3.1 Register Section

2.3.1 Register Section

The main purpose of the control unit is to read and decode instructions from the program memory.
To execute an instruction, the control unit steps through the appropriate blocks of the ALU based on the op-codes contained in the instruction register.
2.3.2 Control Unit

Control Signal Actions
RESET. This input is common to all microprocessors. When this input pin is driven HIGH or LOW (depending on the microprocessor), the program counter is loaded with a predefined address specified by the manufacturer.
2.3.2 Control Unit

Control Signal Actions
READ/WRITE (R/W) This output line is common to all microprocessors. The status of this line tells the other microcomputer elements whether the microprocessor is performing a READ or a WRITE operation. A HIGH signal on this line indicates a READ operation, and a LOW indicates a WRITE operation.
2.3.2 Control Unit

Control Signal Actions
READY, This is an input to a microprocessor. Slow devices (memory and I/O) use this signal to gain extra time to transfer data to or receive data from a microprocessor. The READY signal is usually an active low signal; that is, LOW indicates that the microprocessor is ready. Therefore, when the microprocessor selects a slow device, the device places a LOW on the READY pin. The microprocessor responds by suspending all its internal operations and enters a WAIT state. When the device is ready to send or receive data, it removes the READY signal. The microprocessor comes out of the WAIT state and performs the appropriate operation.
2.3.2 Control Unit

Control Signal Actions
Interrupt Request (INT or IRQ). The external I/O devices can interrupt the microprocessor via this input pin on the microprocessor chip. When this signal is activated by the external devices, the microprocessor jumps to a special program called the interrupt service routine. This program is normally written by the user for performing tasks that the interrupting device wants the microprocessor to carry out. After completing this program, the microprocessor returns to the main program it was executing when the interrupt occurred.
2.3.2 Control Unit

The ALU performs all the data manipulations, such as arithmetic and logic operations, inside a microprocessor. The size of the ALU conforms to the word length of the microcomputer.
ALU Functions:
1.Binary addition and logic operations
2. Finding the one’s complement of data
3. Shifting or rotating the contents of a general-purpose register 1 bit to the left or right through a carry
2.3.3 Arithmetic-Logic Unit

Simple Microprocessor
2.3.4 Functional Representations of Simple and Typical Microprocessors

Buffer Register : Stores any data read from memory for further processing by the ALU.
2.3.4 Functional Representations of Simple and Typical Microprocessors

Typical Microprocessor
2.3.4 Functional Representations of Simple and Typical Microprocessors

The Pentium contains two instruction pipelines: the U-pipe and the V-pipe. The U-pipe can execute all integer and floating-point instructions. The V-pipe can execute simple integer instructions
The Pentium contains two separate cache memories: code cache and data cache.

The control unit performs two basic operations:
instruction interpretation
and instruction sequencing.
2.3.5 Simplified Explanation of Control Unit design

There are two methods for designing a control unit:
2.3.5 Simplified Explanation of Control Unit design

How incrementing the contents of the register by 1 is done in microprogramming
control ??
(see figures in next slides)
2.3.5 Simplified Explanation of Control Unit design

2.3.5 Simplified Explanation of Control Unit design

2.3.5 Simplified Explanation of Control Unit design

2.3.5 Simplified Explanation of Control Unit design

2.3.5 Simplified Explanation of Control Unit design

2.3.5 Simplified Explanation of Control Unit design

The following three steps for completing the instruction:
1.Fetch. The microprocessor fetches (instruction read) the instruction from the main memory (external to the microprocessor) into the instruction register.
2. Decode. The microprocessor decodes or translates the instruction using the control unit. The control unit inputs the contents of the instruction register, and then decodes (translates) the instruction to determine the instruction type.
3. Execute. The microprocessor executes the instruction using the control unit. To accomplish the task, the control unit generates a number of enable signals required by the instruction.
2.4 Program Execution by Conventional Microprocessors

For example, suppose that it is desired to add the contents of two registers, X and Y, and store the result in register Z. To accomplish this, a conventional microprocessor performs the following steps:
1. The microprocessor fetches the instruction into the instruction register.
2. The control unit (CU) decodes the contents of the instruction register.
3. The CU executes the instruction by generating enable signals for the register and ALU sections to perform the following:
a. The CU transfers the contents of registers X and Y from the Register section into the ALU.
b. The CU commands the ALU to ADD.
c. The CU transfers the result from the ALU into register Z of the register section.
2.4 Program Execution by Conventional Microprocessors

Enhancement in 32-bit microprocessors (like Pentium) include : cache memory, memory
management, pipelining, floating-point arithmetic, and branch prediction.
Cache memory is a high-speed read/write memory implemented as on-chip
hardware in typical 32-bit microprocessors in order to increase processing rates. This topic
is covered in more detail in Chapter 3.
2.5 Program Execution by typical 32-bit Microprocessors

Memory management allows programmers to write programs much larger than those that could fit in the main memory space available to the microprocessors; the programs are simply stored on a secondary device, such as a hard disk. This topic is covered in more detail in Chapter 3.
2.5 Program Execution by typical 32-bit Microprocessors

Basic Concept
2.5.1 Pipelining
Hi is Hardware designed to perform activity Ai

2.5.1 Pipelining

Two Kind of Pipelining:
Arithmetic operations and instruction execution.
2.5.1 Pipelining

Arithmetic Pipelines
Consider the process of adding two floating-point numbers x =0.9234 * 104 and y = 0.48 * 10 2.
First: exponents of x and y are unequal.
Second: exponent alignment.
Third: Perform the addition
Fourth: Normalize the final answer
2.5.1 Pipelining

Instruction Pipelines
Instruction cycle typically involves the
following activities:
1. Instruction fetch -?needs five clocks to complete
2. Instruction decode
3. Operand fetch (Data Read)
4. Operation execution
5. Result routing.
2.5.1 Pipelining

Example of the execution of a stream of five instructions: 11,12,13,14, and 15, in which I3 is a conditional branch instruction.
2.5.1 Pipelining

This allows these microprocessors to anticipate jumps of the instruction flow ahead of time.
2.5.2 Branch Prediction Feature

To accomplish this, the Pentium includes on-chip hardware called the Branch Unit (BU). The BU contains the branch execution unit (BEU) and the branch prediction unit (BPU). Whenever the Pentium encounters a conditional branch instruction, it sends it to the BU for execution. The BU evaluates the instruction’s branch condition using the BEU and determines whether the branch should or should not be taken. Once the BU determines the branch condition, it calculates the starting address (Branch target) of the next block of code to be executed. The Pentium then starts fetching code at the new address.
2.5.2 Branch Prediction Feature

Scalar processors such as the 80486 can execute one instruction per cycle.
The 80486 contains only one pipeline.
Superscalar microprocessors, can execute
more than one instruction per cycle. These microprocessors contain more than one pipeline.
The Pentium, a superscalar microprocessor, contains two independent pipelines. This
allows the Pentium to execute two instructions per cycle.
2.6 Scalar and Superscalar Microprocessors

There are two types of microprocessor architectures: RISC and CISC.
RISC stand for (reduced instruction set computer) and CISC for (complex instruction set computer)
2.7 RISC vs. CISC

2.7 RISC vs. CISC

Intel’s original Pentium is a CISC microprocessor. Intel Pentium Pro and other succeeding members of the Pentium family and Motorola 68060 use a combination of RISC and CISC architectures for providing high performance. The Pentium Pro and other succeeding
2.7 RISC vs. CISC

LECTURE 12

• The Requirements of a memory chip
A memory chip requires address lines to identity a memory register.
The number of address lines required is determined by thenumber of registers in a chip(2n = number of registers where n is the number of addresslines).A memory chip requires a Chip Select (CS) signal to enablethe chip. The remaining address lines of themicroprocessor can be connected to the CS signalthrough an interfacing logic.The address lines connected to CS select the chip, and theaddress lines connected to the address lines of the memorychip select the register.° The control signal Read (RD) enables the output buffer,and data from the selected register are made available onthe output lines.° The control signal (WR) enables the input buffer, and dataon the input lines are written into memory cells.

• INPUT AND OUTPUT (I/O) DEVICES :
• Input/output devices are the means through which theMPU communicates with "the outside world.“
• There are two different methods by which I/O devices canbe identified.1. I/Os with 8-Bit Addresses (Peripheral-Mapped I/O)
• The steps in communicating with an I/O deviceThe MPU places an 8-bit address on the address bus.which is decoded by external decode logic.The MPU sends a control signal (I/O Read or I/O Write)and enables the I/O device.Data are transferred using the data bus.2. I/Os with l6-Bit Addresses (Memory-Mapped I/O)the MPU uses 16 address lines to identify an I/O device.This is known as memory-mapped I/O.

• THE 8085 MPUoThe term microprocessing unit (MPU) is similar to theterm central processing unit (CPU) used in traditionalcomputers.MicroProcessing Unit (MPU)A device or a group of devices (as a unit) that cancommunicate with peripherals, provide timing signals,direct data flow, and perform computing tasks asspecified by the instructions in memory.The 8085 microprocessor can almost qualify as an MPUwith the following two limitations.1. The low-order address bus of the 8085 microprocessor ismultiplexed (time-shared) with the data bus. The busesneed to be demultiplexed.2. Appropriate control signals need to be generated tointerface memory and I/O with the 8085.

• THE 8085 AND ITS PIN DESCRIPTION• The 8085 is an 8-bit general purpose microprocessorthat can address 64K Byte of memory.• It has 40 pins and uses +5V for power. It can run at amaximum frequency of 3 MHz.• The pins on the chip can be grouped into 6 groups:Address Bus and Multiplexed Data Bus. ( 16 Pins )Control and Status Signals. ( 6 Pins )Power supply and frequency. ( 4 Pins )Externally Initiated Signals. ( 7 Pins )Interupt Signals. ( 5 pins )Serial I/O ports. ( 2 Pins )

8085 Microprocessor Pin Out Diagram

• Control and Status Signals :-o ALE-Address Latch Enable:This is a positive going pulse generated every time the 8085begins an operation (machine cycle): it indicates that thebits on AD7-AD, are address bits.This signal is used primarily to latch the low-order addressfrom the multiplexed bus and generate a separate set ofeight address lines. A7-A0-o RD-READ :This is a Read control signal (active low).This signal indicates that the selected I/O or memorydevice is to be read and data are available on the data bus.WR-WRITE :This is a Write control signal (active low).This signal indicates that the data on the data bus are tobe written into a selected memory or I/O location.

IO/M :This is a status signal used to differentiate between I/Oand memory operations.When it is high it indicates an I/O operation; when it islow, it indicates a memory operation.This signal is combined with RD (Read) and WR (Write) togenerate I/O and memory control signals.o S, & So :These status signals, similar to IO/M.They can identify various operations, but they are rarelyused in small systems

• Interrupts :Processor has 5 interrupts. They are presented below inthe order of their priority (from lowest to highest):INTR is maskable interrupt. When the interrupt occursthe processor fetches instruction from the bus.RST 5.5 is a maskable interrupt. When this interrupt is… received the processor saves the contents of the PC cregister into stack and branches to 2CH (hexadecimal)address.RST 6.5 is a maskable interrupt. When this interrupt isreceived the processor saves the contents of the PCregister into stack and branches to 34H (hexadecimal)address.

RST 7.5 is a maskable interrupt. When this interrupt isreceived the processor saves the contents of the PCregister into stack and branches to 3CH (hexadecimal)address.TRAP is a non-maskable interrupt. When this interruptis received the processor saves the contents of the PCregister into stack and branches to 24H (hexadecimal)address.All maskable interrupts can be enabled or disabled usingEI and DI instructions.

TIMING SIGNALS FOR FETCHING AN INSTRUCTIONAt T1 , the high order 8 address bits (20H) are placed on>the address lines A8 - A15 and the low order bits areplaced on AD7-ADO.The ALE signal goes high to indicate that AD0 - AD8 arecarrying an address.At exactly the same time, the IO/M signal goes low toindicate a memory operation.At the beginning of the T2 cycle, the low order 8 addressbits are removed from AD7- ADO and the controllersends the Read (RD) signal to the memory.The signal remains low (active) for two clock periods toallow for slow devices.During T2 , memory places the data from the memory>location on the lines AD7- AD0 .

During T3 the RD signal is Disabled (goes high). This turnsoff the output Tri-state buffers in the memory. That makesthe AD7- ADO lines go to high impedence mode.The machine code or the byte (4FH) is decoded by theinstruction decoder, and the contents of theaccumulator are copied into register C. This task isperformed during the period T4

• DEMULTIPLEXING AD7-ADO• From the above description, it becomes obvious thatthe AD7- ADO lines are serving a dual purpose andthat they need to be demultiplexed to get all theinformation.• The high order bits of the address remain on the busfor three clock periods. However, the low order bitsremain for only one clock period and they would belost if they are not saved externally.• Also, notice that the low order bits of the addressdisappear when they are needed most.• To make sure we have the entire address for the fullthree clock cycles, we will use an external latch tosave the value of AD7- ADO when it is carrying theaddress bits. We use the ALE signal to enable thislatch.

Demultiplexing AD7-AD0

Given that ALE operates as a pulse during T1, wewill be able to latch the address. Then when ALEgoes low, the address is saved and the AD7- ADOlines can be used for their purpose as the bi-directional data lines.

• CYCLES AND STATES• From the above discussion, we can define terms thatwill become handy later on:• T- State: One subdivision of an operation. A T-statelasts for one clock period.• An instruction's execution length is usuallymeasured in a number of T-states. (clock cycles).• Machine Cycle: The time required to complete oneoperationofaccessingmemory, I/O,oracknowledging an external request.• This cycle may consist of 3 to 6 T-states.• Instruction Cycle: The time required to complete theexecution of an instruction.• In the 8085, an instruction cycle may consist of 1to 6 machine cycles.

•GENERATING CONTROL SIGNALS• The 8085 generates a single RD signal. However, thesignal needs to be used with both memory and I/O. So,it must be combined with the IO/M signal to generatedifferent control signals for the memory and I/O.• Keeping in mind the operation of the IO/M signal wecan use the following circuitry to generate the right setof signals:

• THE 8085 MACHINE CYCLES• The 8085 executes several types of instructions witheach requiring a different number of operations ofdifferent types. However, the operations can begrouped into a small set.• The three main types are:• Memory Read and Write.• I/O Read and Write.• Request Acknowledge.• These can be further divided into various operations(machine cycles).

• OPCODE FETCH MACHINE CYCLE• The first step of executing any instruction is theOpcode fetch cycle.• In this cycle, the microprocessor brings in theinstruction's Opcode from memory.• To differentiate this machine cycle from the verysimilar "memory read" cycle, the control & statussignals are set as follows:• IO/M=0, s0 and s1 are both 1.• This machine cycle has four T-states.• The 8085 uses the first 3 T-states to fetch theopcode.• T4 is used to decode and execute it.• It is also possible for an instruction to have 6 T-states in an opcode fetch machine cycle.

the memory read machine cycle• To understand the memory read machine cycle, let'sstudy the execution of the following instruction:• MVI A, 322000H3E• In memory, this instruction looks like:2001H32• The first byte 3EH represents the opcode forloading a byte into the accumulator (MVI A), thesecond byte is the data to be loaded.• The 8085 needs to read these two bytes from memorybefore it can execute the instruction. Therefore, it willneed at least two machine cycles.• The first machine cycle is the opcode fetchdiscussed earlier.• The second machine cycle is the Memory ReadCycle.

• MACHINE CYCLES VS. NUMBER OF BYTES INTHE INSTRUCTION• Machine cycles and instruction length, do not have a directrelationship.• To illustrate lets look at the machine cycles needed to executethe following instruction.• STA 2065H• This is a 3-byte instruction requiring 4 machine cycles and 13 T-states.32H 2010-• The machine code will be stored65H 2011Hin memory as shown to the right20H2012H• This instruction requires the following 4 machine cycles:• Opcode fetch to fetch the opcode (32H) from location 2010H,decode it and determine that 2 more bytes are needed (4 T-states).• Memory read to read the low order byte of the address (65H) (3T-states).•• Memory read to read the high order byte of the address (20H) (3T-states).• A• A memory write to write the contents of the accumulator intothe memory location.

LECTURE 13 MICROPROCESSORS

Microprocessors

Input / OutputInput DevicesSwitches , Keyboard , …Output Devices:Seven Segments (LEDs) , printer , Monitor ,…The processor reads the instructions from thememory , data from the input devices,processes them, produces the output

The CPU includes ALU, control Units, and Various Registers

The Von Neumann Model
It uses von Neumann execution cycle
(also called the fetch-decode-execute cycle)

A cycle could be as follows:The control unit fetches the next programinstruction from the memory, using the programcounter to determine where the instruction islocated.The instruction is decoded into a language theALU can understand.Any data operands required to execute theinstruction are fetched from memory and placedinto registers within the CPU.The ALU executes the instruction and places theresults in registers or memory.

Advances in SemiconductorTechnologyIC- Integrated Circuits -> few transistors and diodes onone chipSSI -small scale Integration-> few gates on one chipMSI- Medium scale Integration- 100 gates on a chipLSI - Large Scale Integration - 1000 gates on a chipVLSI - Very large scale IntegrationSLSI - Super Large Scale IntegrationBorders between VLSI and SLSI are not strict.

Microprocessor programming
* Machine language
Instruction written in binary format
Assembly language
Text based format add a, b
*High level language

Z80 instructions and alphanumeric codes

Microprocessor Based System

Microprocessor Unit
Progremmable logic unit with a designed set of instructions

MPU frequently communicates with the memory, I/O devices

What does it needs to do so..

What does it needs to do so…Group of logic circuitsSet of signal to transfer informationControl signals for timingClock circuits

Program-initiated operationsand BusesanMicroprocessor and Memory OperationsMemory ReadReads instructions or data from the memoryMemory WriteWrites instructions and data into memoryI/O ReadAccepts data from input devicesI/O WriteWrites data to output devices

Program-initiated operationsand BusesFrom where to read or to write?We need an address! Right?How the input/output will know about the operation?We need a control signal to tell themMPU Operations Steps:Identify the addressSend synchronization SIGNAL- control signal•Transfer the binary dataSo, how many buses do we need?

BusesAddress BusIdentify the memorylocationsCPU(ALU, Registers,and Control)MemoryInputandOutputData BusData BusHolds the data duringAddress Bustransfer operationControl BusControl Lines° For timing signal

BusesAddress Bus Size - bitsDepends on the number of memory locations thatcan be accessedZ80 has 16 address lines to address 216 locationsData Bus Size - bitsDepends on the data to be transferredZ80 has 8 bits data busWhat is the maximum memory size Z80 can use?

How the MPU Writes into the Memory?•MPU places the 16 bit address on the address busMemory interfacing circuits will decode address tospecify the target registerMPU Places a byte on the data bus• MPU sends a control signal (Memory Write) tothe memory to write

How the MPU reads from the Memory?MPU places the 16 bit address on the address busMemory interfacing circuits will decode address tospecify the target registerMPU sends a control signal (Memory Read) tothe memory to enable the output buffer•The memory puts the data on the data bus and theprocessor will read it

LECTURE 13 MICROPROCESSOR

BusesAddress Bus Size - bitsDepends on the number of memory locations thatcan be accessedZ80 has 16 address lines to address 216 locationsData Bus Size - bitsDepends on the data to be transferredZ80 has 8 bits data bus• What is the maximum memory size Z80 can use?

Externally Initiated operationInterruptions categories :Reset - e. g. timer to reset everything in the MPUInterrupt - stop temporarily and do something , then come back.Wait: the memory can not handle the MPU request , wait signalmust be generated.Bus Request: sometimes the processor is too slow to hand arequest that can be handled faster by another device.E.g transfer large amount of data through the DMA could befaster than using the MPU

LECTURE 14

Microcontrollers
Fundamentals of Logic Design
By Dana Utebayeva

Micro-Controller
A single chip Computer (to some extent)
Has CPU
RAM
EEPROM
I/O in form of pins
Peripherals (Timer , Communication modes , ADC etc)

Background
Line Following Robots
Wireless keyboards
They were made using Microcontrollers

Suppose we want to make a Line following Robot
What do we do ?
Use a computer with 2.4Ghz Intel core I7 with 4 Gb RAM , 500 Gb Hard disk , 1 Gb Graphics Card ??

Why not a Computer ?
PC is a general purpose computer.
Can run thousand of softwares
Microsoft ppt in which you are seeing this presentation
Games (NFS , AOE , Call of Duty)
Highly expensive

Why MCU
Small reflected by the word “MICRO”
Inexpensive
Ideal for doing repetitive tasks
Easy to use
Highly Efficient and fast

Selecting a MCU
Two family of MCU extremely popular
AVR
PIC
We use AVR series of MCU from Atmel
The instructions are fed once in the form of a Hex file

Tools Required -> CVAVR

Compiler -> CVAVR
The code is written in C language so we need to convert it into the format that Atmega understands

Transfer code to Atmega AVR Studio

Avr Programmer

So we need two softwares overall
CVAVR –> Editor and Compiler
Avr Studio –> Transfer Code to Atmega

Atmega 16

Basics of C language
If else block
If(condition)
{
… …
}
else
{
… …
}

While & For
While (conditon)
{
… ...
}
for(initialisation; condition; increment)
{
… …
}

Lets Begin by blinking a simple LED

Circuit Diagram

Getting Started with CVAVR

Open CVAVR
Go to File
New
Project

Open CVAVR

Go to File

Click on New

Select Project- > Click OK

Click YES

Select Chip

Introduction to I/O

Atmega has total of 40 pins out of which 32 pins can be used as Input or Output
These 32 pins are divided into 4 groups of 8 pins PORTA, PORTB , PORTC , PORTD

Data Direction register (DDR)
This sets direction for all pins (32)
Direction for these pins can be Input or Output
To blink an LED we need to set pin as “OUTPUT” but “HOW“ ?
DDRA = 0b00000001 ;
DDRA = 0x01 ;
1 Stands for Output & 0 stands for Input

What is Next ?
We have set the Pin as Output
What else do we need to light the LED ??
Supply of 5 Volts !!! This is given by PORT Register

PORT Register
Only after you have set the Pin to Output you can control them through this Register
It is a 8 bit register . It corresponds to the pin in same manner as that of DDR Register
Used to set output value ( 0 or 1 ) only if the corresponding Pin has been set as output by DDR Register
PORTA= 0b 00000001;
or
PORTA= 0x01 ;
1 stands for 5V
0 stands for 0V
MSB
LSB

Simple Questions
DDRA= 0b 00101100
DDRD = 0xf4
DDRC = 0b 01111110
DDRB = 0x3b
Assume all 32 pins set as output
PORTA = 0b00001100;
PORTD = 0b11110000;
PORTB.4=1;
PORTC.2=1;

Setting I/O

Go to Ports

Click on In to make that pin Output
Can do so for all four ports

Click on File

Generate Save and Exit

Enter name (3 times)

Where is the code stored ?

Then Click Save

Name of Project & Location

Writing the Code

NOTE : We write our code in While block
While (1)
{
PORTA.1=1; // sets the Pin to 5 volts PORTA.1=0; // sets the Pin to 0 volts
}
This makes the LED to blink but we cannot see blinking !!!

This is because Atmega runs at a frequency of 8000000 Hz
We need to introduce delay so as to see blinking
Use header file delay.h
Function to be used ? delay_ms(time in millis); While (1)
{
delay_ms(1000); PORTA.1=1;
delay_ms(1000); PORTA.1=0;
}

How to compile
Code is written in C language but Atmega understands Hex file
so we need to convert the C file to Hex file

Compiling

Make the Project

Check for errors

Hex File
You can find the Hex file in Bin folder or the EXE folder of the directory where You installed CVAVR

So we Have our Code ready
Feed this code to Atmega using Programmer (we will see this in workshop )
Lets see the code in action

Lets add an Input
Most Common Input ? Button
Since we have already made A0 as Input
We connect a button to that pin
If button is pressed light the LED else turn it off
First draw the Circuit Diagram

Circuit Diagram

Never leave any Input pin unconnected / floating at any point of time while your circuit is working
In Last Circuit A0 is floating when button is not pressed so our Circuit Diagram is wrong

What is the Voltage at the Floating PIN ?
Not 5 V
Not 0V
Its UNDEFINED
So never leave an input pin unconnected
Use the Concept of Pull up / Pull down

In Layman terms
PULL DOWN : Gives 0V when unconnected
PULL UP : Gives 5V when unconnected
Connect the PIN to Ground through a resistance for pulling down
Connect the PIN to 5V through a resistance for Pulling up

Correct Circuit Diagram

PIN Register
It is a 8 bit register . It corresponds to the pin in same manner as that of DDR Register
It is used to read voltage at a pin
To be used only after the pin has been set as input by DDR register

Using Pin Register
int a; // Define the variable a to store the value of voltage a=PINA.0; // read value at pin A.0 (make sure it is input)
If (a==1) // if voltage is 5V
{
PORTA.1=1; // Light the LED
}
else
{
PORTA.1=0; // Turn off the LED
}

Code in Action

Microprocessor consists of only a Central Processing Unit, whereas Micro Controller contains a CPU, Memory, I/O all integrated into one chip.
The microprocessor is useful in Personal Computers whereas Micro Controller is useful in an embedded system.
The microprocessor uses an external bus to interface to RAM, ROM, and other peripherals, on the other hand, Microcontroller uses an internal controlling bus.
Microprocessors are based on Von Neumann model Microcontrollers are based on Harvard architecture
The microprocessor is complicated and expensive, with a large number of instructions to process but Microcontroller is inexpensive and straightforward with fewer instructions to process.
1) What is a Microprocessor?
In simple words, The microprocessor is useful in very intensive processes. It only contains a CPU (central processing unit) but there are many other parts needed to work with the CPU to complete a process. These all other parts are connected externally.
Microprocessors are not made for a specific task as well as they are useful where tasks are complex and tricky like the development of software, games, and other applications that require high memory and where input and output are not defined.
Do you understand? I think a bit, but it's ok, let’s understand by some daily life examples
A) Household devices: Complex home security, Home computers, Video game systems and many more.
B) Transportation and Industrial Devices: Automobiles, trains, planes, Computer servers, high tech medical devices, etc.
Did you notice! All the above applications are complex and they need to process all complicated data.
2) What is Microcontroller?
The microcontroller is designed for a specific task or to perform the assigned task repeatedly. Once the program is embedded on a microcontroller chip, it can’t be altered easily and you may need some special tools to reburn it. As per application, the process is fixed in microcontroller. Hence, the output depends on the input given by the user or sensors or predefined inputs.
The applications easily connect with concepts, so let's find out day to day life examples
e.g. Calculator, Washing Machine, ATM machine, Robotic Arm, Camera, Microwave oven, Oscilloscope, Digital multimeter, ECG Machine, Printer so on and so forth.

LECTURE 15 APPLICATIONS OF MICROPROCESSORS MICROCONTROLLERS

Applications of Microprocessors & Microcontrollers
Dana Utebayeva

Outline

Best Processors of PCs and Laptops

Mobile Processor
The mobile processor is used in mobile computers and cell phones. The CPU IC is designed for laptop computers to run without a fan, with a power rating of less than 10-15W, which is cool enough without a fan.

5 chips (in alphabetic order)especially designed for AI
AMD Radeon Instinct
Usage
Radeon Instinct is AMD’s brand of deep learning oriented GPUs. It replaced AMD’s FirePro S brand in 2016. Compared to the Radeon brand of mainstream consumer/gamer products, the Radeon Instinct branded products are intended to accelerate deep learning, artificial neural network, and high-performance computing/GPGPU applications.

Apple A11 Bionic Neural Engine
The Apple A11 Bionic is a 64-bit ARM-based system on a chip (SoC), designed by Apple Inc. and manufactured by TSMC. It first appeared in the iPhone 8, iPhone 8 Plus, and iPhone X. The A11 includes dedicated neural network hardware that Apple calls a “Neural Engine”. This neural network hardware can perform up to 600 billion operations per second and is used for Face ID, Animoji and other machine learning tasks. The neural engine allows Apple to implement neural network and machine learning in a more energy-efficient manner than using either the main CPU or the GPU.

Google Tensor Processing Unit
A tensor processing unit (TPU) is an application-specific integrated circuit (ASIC) developed by Google specifically for machine learning. Compared to a graphics processing unit, it is designed for a high volume of low precision computation (e.g. as little as 8-bit precision) with higher IOPS per watt, and lacks hardware for rasterisation/texture mapping. The chip has been specifically designed for Google’s TensorFlow framework. However, Google still uses CPUs and GPUs for other types of machine learning. Other AI accelerator designs are appearing from other vendors also and are aimed at embedded and robotics markets.

Huawei Kirin 970
Kirin 970 is powered by an 8-core CPU and a new generation 12-core GPU. Built using a 10nm advanced process, the chipset packs 5.5 billion transistors into an area of only one cm². HUAWEI’s flagship Kirin 970 is HUAWEI’s first mobile AI computing platform featuring a dedicated Neural Processing Unit (NPU). Compared to a quad-core Cortex-A73 CPU cluster, the Kirin 970’s heterogeneous computing architecture delivers up to 25x the performance with 50x greater efficiency.

IBM Power9
Recently launched by IBM, Power9 is a chip which has a new systems architecture that is optimized for accelerators used in machine learning. Intel makes Xeon CPUs and Nervana accelerators and NVIDIA makes Tesla accelerators. IBM’s Power9 is literally the Swiss Army knife of ML acceleration as it supports an astronomical amount of IO and bandwidth, 10X of anything that’s out there today

Intel Nervana
The Nervana ‘Neural Network Processor’ uses a parallel, clustered computing approach and is built pretty much like a normal GPU. It has 32 GB of HBM2 memory dedicated in 4 different 8 GB HBM2 stacks, all of which is connected to 12 processing clusters which contain further cores (the exact count is unknown at this point). Total memory access speeds combine to a whopping 8 terabits per second.